An extended class of sequential circuits with combinational test generation complexity

被引：5
|
作者：
Inoue, M [1 ]
Jinno, C [1 ]
Fujiwara, H [1 ]
机构：
[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Nara 63001, Japan
来源：
ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/ICCD.2002.1106770
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We introduce a class of sequential circuits with internally switched balanced structure which allows test generation with combinational test generation complexity. The proposed class includes any other known classes with this feature. This paper also considers faults in hold registers and switches regarded as macros, while any related work does not consider faults in such macros. Experimental results show the effectiveness of using combinational test Generation for the circuits with internally switched balanced structure.
引用
收藏
页码：200 / 205
页数：6
相关论文
共 50 条
  • [1] A new class of sequential circuits with combinational test generation complexity
    Fujiwara, H
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (09) : 895 - 905
  • [2] One More Class of Sequential Circuits having Combinational Test Generation Complexity
    Debesh Kumar Das
    Hideo Fujiwara
    [J]. Journal of Electronic Testing, 2015, 31 : 321 - 327
  • [3] One More Class of Sequential Circuits having Combinational Test Generation Complexity
    Das, Debesh Kumar
    Fujiwara, Hideo
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2015, 31 (03): : 321 - 327
  • [4] Max-testable class of sequential circuits having combinational test generation complexity
    Das, DK
    Inoue, T
    Chakraborty, S
    Fujiwara, H
    [J]. 13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2004, : 342 - 347
  • [5] A class of sequential circuits with combinational test generation complexity under single-fault assumption
    Inoue, M
    Gizdarski, E
    Fujiwara, H
    [J]. PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), 2000, : 398 - 403
  • [6] A new class of sequential circuits with acyclic test generation complexity
    Ooi, Chia Yee
    Fujiwara, Hideo
    [J]. PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2007, : 425 - 431
  • [7] Sequential circuits with combinational test generation complexity under single-fault assumption
    Inoue, M
    Gizdarski, E
    Fujiwara, H
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2002, 18 (01): : 55 - 62
  • [8] Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption
    Michiko Inoue
    Emil Gizdarski
    Hideo Fujiwara
    [J]. Journal of Electronic Testing, 2002, 18 : 55 - 62
  • [9] Combinational test generation for various classes of acyclic sequential circuits
    Kim, YC
    Agrawal, VD
    Saluja, KK
    [J]. INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, : 1078 - 1087
  • [10] Combinational automatic test pattern generation for acyclic sequential circuits
    Kim, YC
    Agrawal, VD
    Saluja, KK
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (06) : 948 - 956
12345