An extended class of sequential circuits with combinational test generation complexity

被引：5
|
作者：
Inoue, M [1 ]
Jinno, C [1 ]
Fujiwara, H [1 ]
机构：
[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Nara 63001, Japan
来源：
ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/ICCD.2002.1106770
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
We introduce a class of sequential circuits with internally switched balanced structure which allows test generation with combinational test generation complexity. The proposed class includes any other known classes with this feature. This paper also considers faults in hold registers and switches regarded as macros, while any related work does not consider faults in such macros. Experimental results show the effectiveness of using combinational test Generation for the circuits with internally switched balanced structure.
引用
收藏
页码：200 / 205
页数：6
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