Research on application of OBDD to test generation of combinational logic circuits

Conventional test generation algorithms for combinational logic circuits make use of backtracking during the search, that results in lowering down their running efficiency. In this paper, by expressing the logic function of every node in the circuits as OBDD, it transform backtracking into solving the graph problem of OBDD, which avoids backtracking and speeds up the test generation. Meanwhile, the application of OBDD to the generation of test sets and determination of necessary assignments has distinct advantages over those conventional algorithms.