Sequential circuits with combinational test generation complexity under single-fault assumption

被引:2
|
作者
Inoue, M [1 ]
Gizdarski, E [1 ]
Fujiwara, H [1 ]
机构
[1] Nara Inst Sci & Technol, Grad Sch Informat Sci, Ikoma 6300101, Japan
基金
日本学术振兴会;
关键词
test generation; combinational circuit; sequential circuit; balanced structure; internally balanced structure;
D O I
10.1023/A:1013728006805
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.
引用
收藏
页码:55 / 62
页数:8
相关论文
共 50 条
  • [1] Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption
    Michiko Inoue
    Emil Gizdarski
    Hideo Fujiwara
    [J]. Journal of Electronic Testing, 2002, 18 : 55 - 62
  • [2] A class of sequential circuits with combinational test generation complexity under single-fault assumption
    Inoue, M
    Gizdarski, E
    Fujiwara, H
    [J]. PROCEEDINGS OF THE NINTH ASIAN TEST SYMPOSIUM (ATS 2000), 2000, : 398 - 403
  • [3] An extended class of sequential circuits with combinational test generation complexity
    Inoue, M
    Jinno, C
    Fujiwara, H
    [J]. ICCD'2002: IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 2002, : 200 - 205
  • [4] A new class of sequential circuits with combinational test generation complexity
    Fujiwara, H
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (09) : 895 - 905
  • [5] Test generation for acyclic sequential circuits with single stuck-at fault combinational ATPG
    Ichihara, H
    Inoue, T
    [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, PROCEEDINGS, 2003, : 1180 - 1181
  • [6] One More Class of Sequential Circuits having Combinational Test Generation Complexity
    Debesh Kumar Das
    Hideo Fujiwara
    [J]. Journal of Electronic Testing, 2015, 31 : 321 - 327
  • [7] One More Class of Sequential Circuits having Combinational Test Generation Complexity
    Das, Debesh Kumar
    Fujiwara, Hideo
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2015, 31 (03): : 321 - 327
  • [8] A method of test generation for acyclic sequential circuits using single stuck-at fault combinational ATPG
    Ichihara, H
    Inoue, T
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (12) : 3072 - 3078
  • [9] SINGLE-FAULT FAULT-COLLAPSING ANALYSIS IN SEQUENTIAL LOGIC-CIRCUITS
    CHEN, JE
    LEE, CL
    SHEN, WZ
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1991, 10 (12) : 1559 - 1568
  • [10] Max-testable class of sequential circuits having combinational test generation complexity
    Das, DK
    Inoue, T
    Chakraborty, S
    Fujiwara, H
    [J]. 13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2004, : 342 - 347