FPGA BASED DESIGN AND ARCHITECTURE OF NETWORK-ON-CHIP ROUTER FOR EFFICIENT DATA PROPAGATION

Network on Chip (NoC) architectures are proposed to address the communication problems and various fabrication issues in block-based design existing in System on Chip (SoC). In this paper, an efficient NoC router architecture is proposed to route the data from one block to other structurally. For proper routing operation, the proposed architecture has bidirectional data transfer capabilities with design of an efficient controller to control and synchronize the overall operations. The FIFO is optimized for efficient handling of the data, which are transferred in different directions. To generate optimized hardware architecture, various optimization techniques are used at the architectural level. As a result, the overall performance of the architecture is improved than the existing architectures which further proved in the comparison table.