An 11,424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture

被引：0
|
作者：
Seto, Daisaku [1 ]
Watanabe, Minoru [1 ]
机构：
[1] Shizuoka Univ, Hamamatsu, Shizuoka 4328561, Japan
来源：
PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 | 2009年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The world's largest 11,424 gate-count dynamic optically reconfigurable gate array VLSI chip, which is based on the use of junction capacitance of photodiodes as configuration memory, has been fabricated. The size and process of the VLSI chip are, respectively, a 96.04 mm(2) and a 0.35 mu m-3 metal CMOS process technology. To clarify the availability of the VLSI, this paper shows an experimental result of a long retention time of its photodiode memory architecture.
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页码：117 / 118
页数：2
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