High-Throughput Parallel Architecture for H.265/HEVC Deblocking Filter

A novel parallel VLSI architecture is proposed in order to improve the performance of the H.265/HEVC deblocking filter. The overall computation is pipelined, and a new parallel-zigzag processing order is introduced to achieve high throughput. The processing order of the filter is efficiently rearranged to process the horizontal edges and vertical edges at the same time. The proposed H.265/HEVC deblocking filter architecture improves the parallelism by dissolving the data dependency between the adjacent filtering operations. Our design is also compatible with H.264/AVC. Experimental results demonstrate that our architecture shows the best performance compared with other architectures known so far at the expense of the slightly increased gate count. We improve the performance by 52.3%, while the area is increased by 25.8% compared with the previously known best architecture for H.264/AVC. The operating clock frequency of our design is 226 MHz in TSMC LVT 65 process. The proposed design delivers the performance to process 1080p HD at 60 fps.