An effective software pipelining algorithm for clustered embedded VLIW processors

被引:0
|
作者
Akturan, C [1 ]
Jacome, MF [1 ]
机构
[1] Univ Texas, Dept Elect & Comp Engn, Austin, TX 78712 USA
基金
美国国家科学基金会;
关键词
clustering; embedded systems; optimizingcompilers; retiming; soft real-time applications; software pipelining; VLIW processor;
D O I
10.1023/A:1019799515784
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW processors. CALiBeR can be used by embedded system designers to explore different code optimization alternatives, that is, high-quality customized retiming solutions for desired throughput and program memory size requirements, while minimizing register pressure. An extensive set of experimental results is presented, demonstrating that our algorithm compares favorably with one of the best state-of-the-art algorithms, achieving up to 50% improvement in performance and up to 47% improvement in register requirements. In order to empirically assess the effectiveness of clustering for high ILP applications, additional experiments are presented contrasting the performance achieved by software pipelined kernels executing on clustered and on centralized machines.
引用
收藏
页码:113 / 136
页数:24
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