CALiBeR: A software pipelining algorithm for clustered embedded VLIW processors

被引:16
|
作者
Akturan, C [1 ]
Jacome, MF [1 ]
机构
[1] Univ Texas, Dept Elect & Comp Engn, Austin, TX 78712 USA
关键词
D O I
10.1109/ICCAD.2001.968606
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW processors. CALiBeR can be effectively used by embedded system designers to explore different code optimization alternatives, i.e., can assist the generation of high-quality customized retiming solutions for desired program memory size and throughput requirements, while minimizing register pressure. An extensive set of experimental results is presented, considering several representative benchmark loop kernels and a wide variety of clustered datapath configurations, demonstrating that our algorithm compares favorably with one of the best state-of-the-art algorithms, achieving up to 50% improvement in performance and up to 47% improvement in register requirements.
引用
收藏
页码:112 / 118
页数:7
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