Parametric yield estimation for deep sub-micron VLSI circuits

被引：0
|
作者：
Jess, J [1 ]
机构：
[1] Tech Univ Eindhoven, NL-5600 MB Eindhoven, Netherlands
来源：
15TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/SBCCI.2002.1137689
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：387 / 388
页数：2
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