Timing driven Power Gating

被引：23

作者：

Chiou, De-Shiuan ^{[1
]}

Chen, Shih-Hsin ^{[1
]}

Chang, Shih-Chieh ^{[1
]}

Yeh, Chingwei ^{[2
]}

机构：

[1] Natl Tsing Hua Univ, Dept CS, Hsinchu, Taiwan

[2] Natl Chung Cheng Univ, Dept EE, Chiayi, Taiwan

来源：

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年

关键词：

performance; design; leakage current; power gating; IR drop;

D O I：

10.1109/DAC.2006.229189

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this paper, we propose a new methodology for determining the size of sleep transistors for the DSTN structure. We present novel algorithms and theorems for efficiently estimating a tight upper bound of the voltage drop. We also present efficient heurists for minimizing the sizes of sleep transistors. Our experimental results are very exciting.

引用

页码：121 / +

页数：2

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