Maximizing Power Saving Through State-Driven Clock Gating

Toggling driven clock gating has been widely used in industry to save the dynamic power consumed in circuits. However, its big burden is the additional allocation of the expensive XOR cells, which are essentially required to detect if the individual flip-flops will toggle or not at the next clock cycle. Recently, a technique called state-driven clock gating has been proposed to avoid the use of XORs, resulting in reaping more power saving. However, as yet the concept of state-driven clock gating has not been fully and effectively implemented in a way to deliver a maximal power saving since the implementation disallows to group 0-state flip-flops with 1-state flip-flops together for clock gating. This work overcomes this limitation. Precisely, we propose an area-efficient but power-effective logic structure for supporting state-driven clock gating, which is able to group 0-state flip-flops with 1-state flip-flops for clock gating so as to provide achieving a maximal power saving. In the meantime, through experiments with benchmark circuits, it is shown that our proposed state-driven clock gating logic is able to reduce the amount of dynamic and leakage power consumption by 5.8% and 4.7%, respectively over that by the conventional state-driven clock gating logic.