Power Gating in Asynchronous Micropiplines for Low Power Data Driven Computing

In this work we explore the extent at which power gating in asynchronous micropipelines is beneficial at low operating voltages at different input data rates. In addition we present a further improvement to previous techniques by adding the delay blocks to the power gated voltage domains to reduce the leakage energy consumed by these blocks. An asynchronous FIR filter with 4 phase bundled data handshake protocol is presented with and without power shutoff. Implementation is done in 90nm CMOS and simulations performed at 600mV with different input data rates and the total energy consumption recorded. It was noted that at lower data rates, the circuit design with fine grained power gating is energy efficient while at higher data rates it consumes more energy than one without power gating. Our design achieves a total energy saving of 43% at 1KHz input data rate compared to 31% for the previous technique.