共 50 条
- [2] VLSI architecture for 1-D discrete wavelet/wavelet packet transform Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 1999, 20 (03): : 206 - 213
- [3] A scalable architecture for 2-D discrete wavelet transform VLSI SIGNAL PROCESSING, IX, 1996, : 369 - 377
- [4] A new architecture for the 2-D discrete wavelet transform 1997 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2: PACRIM 10 YEARS - 1987-1997, 1997, : 481 - 484
- [5] An efficient architecture for 1-D discrete biorthogonal wavelet transform 2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 697 - 700
- [6] Bit-level systolic imlementation of 1-D and 2-D discrete wavelet transform IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2005, 152 (01): : 25 - 32
- [7] A novel VLSI architecture for 2-d discrete wavelet transform ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 40 - 43
- [8] A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform Journal of VLSI signal processing systems for signal, image and video technology, 1998, 18 : 125 - 140
- [9] An efficient architecture for the 2-D biorthogonal discrete wavelet transform 2001 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL III, PROCEEDINGS, 2001, : 314 - 317
- [10] A VLSI architecture for separable 2-D Discrete Wavelet Transform JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1998, 18 (02): : 125 - 140