共 50 条
- [31] Cost-effective and low-power memory address bus encodings PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2010 - 2013
- [32] Increasing the locality of memory access patterns by low-overhead hardware address relocation PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS, 2003, : 385 - 388
- [34] Exploiting stability to reduce time-space cost for memory tracing COMPUTATIONAL SICENCE - ICCS 2003, PT III, PROCEEDINGS, 2003, 2659 : 966 - 975
- [35] Exploiting Program Cyclic Behavior to Reduce Memory Latency in Embedded Processors APPLIED COMPUTING 2008, VOLS 1-3, 2008, : 1482 - 1486
- [36] Exploiting a computation reuse cache to reduce energy in network processors HIGH PERFORMANCE EMBEDDED ARCHITECTURES AND COMPLIERS, PROCEEDINGS, 2005, 3793 : 251 - 265
- [37] Energy-Aware Real-Time Task Scheduling Exploiting Temporal Locality IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, E93D (05): : 1147 - 1153
- [38] Exploring DDR4 address bus design for high speed memory interface 2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 1843 - 1848