Cu/barrier CMP on porous low-k based interconnect schemes

被引：19

作者：

Gottfried, K.

Schubert, I.

Schulz, S. E.

Gessner, T.

机构：

[1] Fraunhofer Inst Microintegrat & Reliabil, D-09126 Chemnitz, Germany

[2] Tech Univ Chemnitz, Ctr Microtechnol, D-09107 Chemnitz, Germany

来源：

MICROELECTRONIC ENGINEERING | 2006年 / 83卷 / 11-12期

关键词：

CMP; Cu/barrier CMP; low-k; low-k material; low-k dielectrics; porous low-k materials; damascene architecture;

D O I：

10.1016/j.mee.2006.10.007

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Dielectric stacks containing porous low-k materials were investigated regarding their ability to pass CMP processes as used in Cu interconnect technology. Beside the low-k material itself, the impact of layout, cap layer materials and different diffusion barrier materials has been proven. Advanced consumables, partly specially designed for future technology nodes, have been tested within these experiments. Compatibility of the slurries with the low-k stacks, dishing and erosion, impact of polishing parameters like down force and platen speed on low-k stack integrity were examined. Low-k stacks based on a porous MSQ material capped with PECVD-SiC or with a MSQ-hard mask were found to be promising candidates. Low-k stacks based on porous SiO2-aerogel could not meet the stability requirements at present and need additional efforts for adhesion enhancement between cap layer and porous material. Consumables used within the experiments enable an efficient processing with low dishing and erosion as well as an excellent surface quality. (c) 2006 Elsevier B.V. All rights reserved.

引用

页码：2218 / 2224

页数：7

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