Design of a 11 bit 10Ms/s pipelined A/D converter

被引：0
|
作者：
Peng, BL [1 ]
Cheng, J [1 ]
Chen, GC [1 ]
机构：
[1] Xian Jiaotong Univ, Inst Microelect, Xian 710049, Peoples R China
来源：
2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/ICASIC.2001.982561
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 11 bit 10Ms/s A/D Converter (ADC) is presented. The converter consists of a five-stage pipelined architecture and adopts the negative redundant digital correction technique to correct errors in the gain and offset. The fully differential circuitry is used to improve the power supply rejection and reduce errors resulting from the charge injection. The ADC is designed in a 0.6um CMOS technology and dissipates 50mW with a 3v power supply.
引用
收藏
页码：310 / 313
页数：4
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