A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC Decoder in 65nm CMOS

被引：0
|
作者：
Chen, Zhixiang [1 ]
Peng, Xiao [1 ]
Zhao, Xiongxin [1 ]
Okamura, Leona [1 ]
Zhou, Dajiang [1 ]
Goto, Satoshi [1 ]
机构：
[1] Waseda Univ, Grad Sch Informat Prod & Syst, Tokyo, Japan
来源：
2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2013年
基金：
日本学术振兴会;
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.
引用
收藏
页码：87 / 88
页数：2
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