Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

被引：0

作者：

Buergin, Felix ^{[1
]}

Carbognani, Flavio ^{[1
]}

Hediger, Martin ^{[2
]}

Meier, Hektor ^{[2
]}

Meyer-Piening, Robert ^{[2
]}

Santschi, Rafael ^{[2
]}

机构：

[1] ETH, Intergrated Syst Lab IIS, CH-8092 Zurich, Switzerland

[2] IIS, Zurich, Switzerland

来源：

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年

关键词：

algorithms; design; measurement; hearing aids; low-power architecture; speech enhancement;

D O I：

10.1109/DAC.2006.229289

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60 mW in a 0.25 mu m CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42 mW) and the isomorphic architecture (1.54 mW), without overly large area overhead (0.77 mm(2) against 0.43 mm(2) and 4.31 mm(2) respectively).

引用

页码：558 / +

页数：2

共 50 条

[21] SmartAid: A Low-Power Smart Hearing Aid For Stutterers
Scherer, Moritz
Menachery, Kiran
Magno, Michele
2019 IEEE SENSORS APPLICATIONS SYMPOSIUM (SAS), 2019,
[22] Speech quality and stable gain trade-offs in adaptive feedback cancellation for hearing aids
Lee, Ching-Hua
Kates, James M.
Rao, Bhaskar D.
Garudadri, Harinath
JOURNAL OF THE ACOUSTICAL SOCIETY OF AMERICA, 2017, 142 (04): : EL388 - EL394
[23] MATCHING DSP ALGORITHM TRANSFORMATIONS FOR POWER, PERFORMANCE AND MEMORY TRADE-OFFS
Stuikys, Vytautas
Damasevicius, Robertas
Toldinas, Jevgenijus
Ziberkas, Giedrius
INFORMATION TECHNOLOGIES' 2009, 2009, : 178 - 186
[24] Evaluating power-performance trade-offs of VLSI transceiver architecture for low-energy communication system design
Hong, Sangjin
Stark, Wayne E.
IEEE Pacific RIM Conference on Communications, Computers, and Signal Processing - Proceedings, 1999, : 250 - 253
[25] Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm
Kincses, Z.
Voeroeshazi, Zs
Nagy, Z.
Szolgay, P.
Laviniu, T.
Gacsadi, A.
2012 13TH INTERNATIONAL WORKSHOP ON CELLULAR NANOSCALE NETWORKS AND THEIR APPLICATIONS (CNNA), 2012,
[26] A fast, low-power logarithm approximation with CMOS VLSI implementation
SanGregory, SL
Brothers, C
Gallagher, D
Siferd, R
42ND MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2, 1999, : 388 - 391
[27] Power Versus Quality Trade-offs for Adaptive Real-Time Applications
Nelson, Andrew
Akesson, Benny
Molnos, Anca
te Pas, Sjoerd
Goossens, Kees
2012 IEEE 10TH SYMPOSIUM ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA (ESTIMEDIA), 2012, : 75 - 84
[28] Low-Power Digital Signal Processor Design for a Hearing Aid
Shaer, Lama
Nahlus, Ihab
Merhi, Jawad
Kayssi, Ayman
Chehab, Ali
2013 4TH ANNUAL INTERNATIONAL CONFERENCE ON ENERGY AWARE COMPUTING SYSTEMS AND APPLICATIONS (ICEAC), 2013, : 40 - 44
[29] Power/area trade-offs in low-power/low-area unary-R-2R CMOS digital-to-analog converters
Nejati, Babak
Larson, Larry
2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1473 - +
[30] Power-Performance Versus Algorithmic Trade-offs in the Implementation of Wireless Multimedia Terminals
Nooshabadi, Saeid
53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 700 - 703

← 1 2 3 4 5 →