Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm

被引：0

作者：

Buergin, Felix ^{[1
]}

Carbognani, Flavio ^{[1
]}

Hediger, Martin ^{[2
]}

Meier, Hektor ^{[2
]}

Meyer-Piening, Robert ^{[2
]}

Santschi, Rafael ^{[2
]}

机构：

[1] ETH, Intergrated Syst Lab IIS, CH-8092 Zurich, Switzerland

[2] IIS, Zurich, Switzerland

来源：

43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年

关键词：

algorithms; design; measurement; hearing aids; low-power architecture; speech enhancement;

D O I：

10.1109/DAC.2006.229289

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper analyzes the power-area trade-off of functionally equivalent architectural implementations of a speech enhancement algorithm for hearing aids. Gate-level simulations and measurements show that an optimum degree of resource sharing (0.60 mW in a 0.25 mu m CMOS process) is more energy-efficient than both the fully time-multiplexed (1.42 mW) and the isomorphic architecture (1.54 mW), without overly large area overhead (0.77 mm(2) against 0.43 mm(2) and 4.31 mm(2) respectively).

引用

页码：558 / +

页数：2

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