The design of highly-parallel image processing systems using nanoelectronic devices

As minimum device dimensions are reduced from a few hundred nm to a few nm the number of devices on a single small chip will rise from one million to ten billion. However, as dimensions are reduced below approximately 100 nm, device characteristics will all differ from those of current devices. The anticipated packing density (and performance) of such nanoelectronic devices could be usefully applied in the achievement of highly-parallel, highly-compact, computer systems but, because of the changes anticipated in device characteristics, the designs of such systems need to be reevaluated. This paper describes the re-evaluation of the data-parallel SIMD type of system in the light of a perceived problem concerning the difficulty of conveying signals over long distances on nanoscale wires. To overcome this problem, a novel architecture, the Propagated Instruction Processor, has been developed which incorporates design elements from SIMD arrays, pipelines and systolic architectures. Examples of circuit elements, suitable for incorporation in such an architecture, implemented in QCA components are presented together with the results of simulations which demonstrate the potential packing density and performance of such systems.(1).