Trench DRAM technologies for the 50nm node and beyond

被引：0

作者：

Mueller, W. ^{[1
]}

Aichmayr, G. ^{[1
]}

Goldbach, M. ^{[1
]}

Hecht, T. ^{[1
]}

Kudelka, S. ^{[1
]}

Lau, F. ^{[2
]}

Nuetzel, J. ^{[1
]}

Orth, A. ^{[1
]}

Schloesser, T. ^{[1
]}

Scholz, A. ^{[1
]}

Sieck, A. ^{[1
]}

Spitzer, A. ^{[2
]}

Strasser, M. ^{[2
]}

Wand, P. -F. ^{[1
]}

Wege, S. ^{[1
]}

Weis, R. ^{[1
]}

机构：

[1] Infineon Technol, D-01099 Dresden, Germany

[2] Infineon Technol, D-81609 Munich, Germany

来源：

2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper reviews the DRAM technology challenges for overcoming the 50nm barrier. First the product requirements and barriers to shrink the DRAM cell beyond 50nm will be addressed. Then the technology solutions for DRAM cell capacitor, cell transistor, and support transistors will be presented. Key enablers are high aspect ratio cell capacitor structures, new capacitor materials, 3-dimensional cell transistor schemes and high performance LSTP support device technologies.

引用

页码：92 / +

页数：2

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