Serial low power bus coding for VLSI

被引：3

作者：

Kuo, Chih-Hung ^{[1
]}

Wu, Wey-Bang ^{[1
]}

Wu, Yi-Jang ^{[1
]}

Lin, Jia-Hung ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, 1 Univ Rd, Tainan 70101, Taiwan

来源：

2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4: VOL 1: SIGNAL PROCESSING | 2006年

关键词：

D O I：

10.1109/ICCCAS.2006.285171

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, we present a serial coding method to reduce the bus transition activity and implement error control code to reduce bit error probability. We propose two kinds of coding method for data bus. The basic principle is to append extra information pattern to the back of the original data packet. Experimental results show that the proposed coding scheme can reduce total bus transitions by 12% on the average, compared to that of the uncoded patterns, without adding redundant bitlines on the bus.

引用

页码：2449 / 2453

页数：5

共 50 条

[1] Preceded two-dimensional coding method for low-power serial bus
Shin, Y
Jeong, DK
ELECTRONICS LETTERS, 1999, 35 (18) : 1524 - 1526
[2] Serial bus encoding for low power application
Saneei, Mohsen
Afzali-Kusha, Ali
Navabi, Zainalabedin
2006 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP PROCEEDINGS, 2006, : 99 - +
[3] A novel bus encoding technique for low power VLSI
Natesan, J
Radhakrishnan, D
ESA'04 & VLSI'04, PROCEEDINGS, 2004, : 54 - 59
[4] A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects
Sainarayanan, K. S.
Ravindra, J. V. R.
Srinivas, M. B.
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 4155 - +
[5] Minimal redundancy, low power bus coding
Lindkvist, Tina
Lofvenberg, Jacob
NORCHIP 2005, PROCEEDINGS, 2005, : 277 - 280
[6] Bus architecture for low-power VLSI digital circuits
Cardarilli, GC
Salmeri, M
Salsano, A
Simonelli, O
ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 21 - 24
[7] Shift invert coding (SINV) for low power VLSI
Natesan, J
Radhakrishnan, D
PROCEEDINGS OF THE EUROMICRO SYSTEMS ON DIGITAL SYSTEM DESIGN, 2004, : 190 - 194
[8] A Two-bit Bus-Invert Coding Scheme With a Mid-level State Bus-Line for Low Power VLSI Design
Yoon, Myungchul
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2014, 14 (04) : 436 - 442
[9] A novel low-power bus design for bus-invert coding
Yoon, Myungchul
Roh, Byeong-Hee
IEICE TRANSACTIONS ON ELECTRONICS, 2007, E90C (04) : 731 - 734
[10] Serial-Link Bus: A Low-Power On-Chip Bus Architecture
Ghoneima, Maged
Ismail, Yehea
Khellah, Muhammad M.
Tschanz, James
De, Vivek
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (09) : 2020 - 2032

← 1 2 3 4 5 →