共 50 条
- [3] Weight-based bus-invert coding for low-power applications [J]. ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, : 121 - 125
- [4] Bus-invert coding for low-power I/O - A decomposition approach [J]. PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 750 - 753
- [5] Bus-Invert Coding as a Low-Power Countermeasure Against Correlation Power Analysis Attack [J]. 2019 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM LEVEL INTERCONNECT PREDICTION (SLIP), 2019,
- [7] Partial bus-invert coding for power optimization of system level bus [J]. 1998 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - PROCEEDINGS, 1998, : 127 - 129
- [8] Reduction of bus transitions with partial bus-invert coding [J]. ELECTRONICS LETTERS, 1998, 34 (07) : 642 - 643
- [10] Theoretical analysis of bus-invert coding [J]. PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 742 - 745