On the design of modulo 2n±1 adders

被引：0

作者：

Efstathiou, C ^{[1
]}

Vergos, HT ^{[1
]}

Nikolos, D ^{[1
]}

机构：

[1] TEI Athens, Dept Informat, Athens 12210, Greece

来源：

ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS | 2001年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper we present new architectures for the design of modulo 2(n)+/-1 adders, which are based on the use of the same design block. Our design block incorporates a parallel-prefix carry computation unit with a carry increment stage. VLSI implementations of the proposed architectures in a static CMOS technology reveal their superiority against all already known architectures when the area * time(2) product is used as a metric and n > 8.

引用

页码：517 / 520

页数：4

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