On the detection of reset faults in synchronous sequential circuits

We consider the problem of testing reset faults in synchronous sequential circuits with reset hardware. The reset hardware is assumed to consist of a reset input connected to all the flip-flops through a reset Line. We propose a fault model that accommodates any routing of the reset line to the flip-flops. This is important since test generation is typically carried out without knowledge of the way in which the reset line is routed. We describe fault simulation procedures for the proposed reset fault model. The procedures use a given test sequence and generate appropriate reset sequences, if needed. It is shown that contrary to the common assumption that reset faults are easily detected by test sequences For other faults in the circuit, some reset faults require special reset sequences and special test sequences. Thus, a complete test sequence must explicitly accommodate reset faults.