Cu/Low-k TBGA Glob Top Package Reliability Challenges

被引：0

作者：

Beng, Lau Teck ^{[1
]}

Teck, Siong Chin ^{[1
]}

Lee, Chu-Chung ^{[1
]}

机构：

[1] Freescale Semicond Malaysia Sdn Bhd, Pj 47000, Selangor, Malaysia

来源：

IEMT 2006: 31ST INTERNATIONAL CONFERENCE ON ELECTRONICS MANUFACTURING AND TECHNOLOGY | 2006年

关键词：

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Moving into low-k die packaging era, due to much weaker mechanical properties and poorer adhesion of interlayer dielectric, package reliability always poises a challenge to backend assembly process. This is especially critical for the cavity down Tape Ball Grid Array (TBGA) package. This paper discusses the approach taken to identify a feasible combination of material set and also the various process and design aspects that are important to lessen the overall package stress exerted onto the low-k die during reliability stress, primarily during temperature cycle test. Series of evaluations were conducted to derive a proven good solution for 44um fine pitch wire package and for Pb-free requirement.

引用

页码：294 / 299

页数：6

共 50 条

[21] Cavity-down thermal-enhanced package reliability evaluation for Low-k dielectric/Cu interconnects IC
Tsao, PH
Huang, C
Lin, A
Lii, MJ
Perng, DJ
Tsai, NS
54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1191 - 1193
[22] Structural design for Cu/low-K larger die flip chip package
Biswas, Kalyan
Liu, Shiguo
Zhang, Xiaowu
Chai, T. C.
Chong, Ser-Choong
EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2006, : 237 - 242
[23] Investigation of interconnect design on Chip package interaction and mechanical reliability of Cu/low-k multi-layer interconnects in flip chip package
Uchibori, Chihiro J.
Zhang, Xuefeng
Ho, Paul S.
Nakamura, Tomoji
PROCEEDINGS OF THE IEEE 2008 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2008, : 150 - 152
[24] Reliability challenges for copper low-k dielectrics and copper diffusion barriers
Tokei, Z
Li, YL
Beyer, GP
MICROELECTRONICS RELIABILITY, 2005, 45 (9-11) : 1436 - 1442
[25] Reliability challenges accompanied with interconnect downscaling and ultra low-k dielectrics
Hoofman, RJOM
Michelon, J
Bancken, PHL
Daamen, R
Verheijden, GJAM
Arnal, V
Hinsinger, O
Gosset, LG
Humbert, A
Besling, WFA
Goldberg, C
Fox, R
Michaelson, L
Guedj, C
Guillaumond, JF
Jousseaume, V
Arnaud, L
Gravesteijn, DJ
Torres, J
Passemard, G
PROCEEDINGS OF THE IEEE 2005 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2005, : 85 - 87
[26] Effect of Post-Annealing on Reliability of Cu/Low-k Interconnects
Cheng, Yi-Lung
Lee, Chih-Yen
Chen, Giin-Shan
Fang, Jau-Shiung
ECS JOURNAL OF SOLID STATE SCIENCE AND TECHNOLOGY, 2020, 9 (05)
[27] Electrical reliability issues of integrating low-K dielectrics with Cu metallization
Wu, ZC
Shiung, ZW
Wang, CC
Fang, KL
Wu, RG
Liu, YL
Tsui, BY
Chen, MC
Chang, W
Chou, PF
Jang, SM
Yu, CH
Liang, MS
PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2000, : 82 - 84
[28] The effect of methylating treatments on the dielectric reliability of low-k/Cu structures
Borthakur, S
Satyanarayana, S
Knorr, A
Ho, PS
Materials, Technology and Reliability of Advanced Interconnects-2005, 2005, 863 : 195 - 200
[29] Quantitative projections of reliability and performance for low-k/Cu interconnect systems
Banerjee, Kaustav
Mehrotra, Amit
Hunter, William
Saraswat, Krishna C.
Goodson, Kenneth E.
Wong, S.Simon
Annual Proceedings - Reliability Physics (Symposium), 2000, : 354 - 358
[30] CVD barriers for Cu with nanoporous ultra low-k: Integration and reliability
Lin, JC
Augur, R
Shue, SL
Yu, CH
Liang, MS
Vijayendran, A
de Felipe, TS
Danek, M
PROCEEDINGS OF THE IEEE 2002 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2002, : 21 - 23

← 1 2 3 4 5 →