CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning

被引：3

作者：

Zamanlooy, Babak ^{[1
]}

Mirhassani, Mitra ^{[1
]}

机构：

[1] Univ Windsor, Dept Elect & Comp Engn, Windsor, ON N9B 3P4, Canada

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2015年 / 23卷 / 11期

关键词：

Continuous valued number system (CVNS); multiplier; neural networks; neurochips; noise-to-signal-ratio (NSR); on-chip learning; NEURAL-NETWORK; HARDWARE IMPLEMENTATION; SENSITIVITY; QUANTIZATION; SYSTEM; FPGA; MLP;

D O I：

10.1109/TVLSI.2014.2367496

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Designing low noise-to-signal-ratio (NSR) structures is one of the main concerns when implementing hardware-based neural networks. In this paper, a new continuous valued number system (CVNS) multiplication algorithm for low-resolution environment is proposed with accurate results. Using the proposed CVNS multiplication algorithm, VLSI implementation of a high-resolution mixed-signal CVNS synapse multiplier for neurochips with on-chip learning is realized. The proposed CVNS multiplication algorithm provides structures with lower NSR. Therefore, the proposed CVNS multiplication algorithm can be exploited to design robust CVNS Adaline for neurochips with on-chip learning.

引用

页码：2540 / 2551

页数：12

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