Through-Silicon Capacitor Interconnection for High-Frequency 3-D Microsystem

被引:3
|
作者
Shan, Guangbao [1 ]
Lu, Qijun [1 ]
Liu, Song [2 ]
Yang, Yintang [1 ]
机构
[1] Xidian Univ, Sch Microelect, Shaanxi Key Lab Integrated Circuits & Syst, Xian 710071, Shaanxi, Peoples R China
[2] TSMC, Dept Innovat & Design Optimizat, Nanjing 211806, Jiangsu, Peoples R China
基金
中国国家自然科学基金;
关键词
3-D microsystem; 3-D wireless interconnection; capacitive coupling interconnection (CCI); through-silicon capacitor (TSC); through-silicon via (TSV); PERFORMANCE ANALYSIS; WAFER-LEVEL; OPTIMIZATION; CHALLENGES; BACKSIDE; DESIGN;
D O I
10.1109/TCPMT.2018.2879977
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper presents a novel 3-D capacitive interconnection technology for a 3-D microsystem, which is called through-silicon capacitor (TSC). Two vias similar to through-silicon via (TSV) are bonded vertically by one oxide bonding layer to form the capacitive coupling. Without the adoption of the backside via revealing process, the complicated back-thinning process for TSC will be reduced further, resulting in the lower cost and lower yield loss for 3-D microsystem. Finite-element analysis indicates that under the same dimensions, TSC has much stronger capacitive coupling effect than conventional capacitive coupling interconnect does. Then, SPICE simulation is carried out and demonstrates that a TSC channel with the radius of 2.5 mu m, the height of 30-mu m via, and the thickness of 1-mu m bonding layer can achieve 4-Gb/s data rate and consumes only 0.08 mW/(Gb/s). Moreover, the high-frequency analysis shows that the far-end crosstalk induced by TSC is superior to that induced by TSV. Finally, the potential applications, features, advantages, and disadvantages of TSC, TSV, and capacitive coupling interconnection (CCI) technologies are compared.
引用
收藏
页码:1310 / 1318
页数:9
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