共 50 条
- [21] The Modeling of DC Current Crowding for Through-silicon Via in 3-D IC [J]. 2015 16TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, 2015,
- [22] Sensitivity Analysis of Through-Silicon Via (TSV) Interconnects for 3-D ICs [J]. 2011 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2011,
- [24] Structural Integrity of 3-D Metal-Insulator-Metal Capacitor Embedded in Fully Filled Cu Through-Silicon via [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2021, 11 (06): : 918 - 921
- [25] 3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2013, 3 (02): : 221 - 228
- [28] Study on copper protrusion of through-silicon via in a 3-D integrated circuit [J]. MATERIALS SCIENCE AND ENGINEERING A-STRUCTURAL MATERIALS PROPERTIES MICROSTRUCTURE AND PROCESSING, 2019, 755 : 66 - 74
- [30] A 3-D ELECTROMAGNETIC SIMULATOR FOR HIGH-FREQUENCY APPLICATIONS [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1995, 18 (01): : 112 - 118