Impact of back gate bias on hot-carrier effects of n-channel tri-gate FETs (TGFETs)

被引：0

作者：

Lin, Chia-Pin ^{[1
]}

Tsui, Bing-Yue ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Dept Elect Engn, Room ED630,1001,Ta Hsueh Rd, Hsinchu, Taiwan

来源：

2006 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS | 2006年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The hot-carrier effects of non-planar tri-gate SOI FET (TGFET) with back-gate bias were investigated. Negative back gate bias could raise the influence of buried oxide defects and then degrade the device quickly. For TGFETs with ultra-narrow fin width and side gate extension, the smaller buried oxide interface area and more obvious screening effect terminate the field lines to obviate the back gate bias efficiently. The extrapolated hot-carrier lifetime encourages the TGFETs as promising sub-10nm devices.

引用

页码：82 / +

页数：2

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