Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations

被引：1

作者：

Fukazawa, Mitsuya ^{[1
]}

Kurimoto, Masanori ^{[2
]}

Akiyama, Rei ^{[3
]}

Takata, Hidehiro ^{[2
]}

Nagata, Makoto ^{[1
,4
]}

机构：

[1] Kobe Univ, Grad Sch Engn, Dept Comp Sci & Syst Engn, Kobe, Hyogo 6578501, Japan

[2] Renesas Technol Corp, Itami, Hyogo 6640005, Japan

[3] Renesas Design Corp, Itami, Hyogo 6640005, Japan

[4] CREST, Tokyo 1020075, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 04期

关键词：

power supply voltage noise built-in probing circuit; failure susceptibility; dynamic frequency; scaling;

D O I：

10.1587/transele.E92.C.475

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.

引用

页码：475 / 482

页数：8

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