Reducing the impact of power supply noise on microprocessor performance

被引：0

作者：

Rahal-Arabi, T ^{[1
]}

Wong, KL ^{[1
]}

Ma, M ^{[1
]}

Barkatullah, J ^{[1
]}

Taylor, G ^{[1
]}

机构：

[1] Intel Corp, Mobile Platform Architecture Dev, Beaverton, OR 97006 USA

来源：

Electrical Performance of Electronic Packaging | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper we demonstrate that it is possible to design circuits insensitive to power supply noise at frequencies in the range of 200 MHz to 500 MHz. We show that by using proper filter design at the beginning of the clock distribution network we increase the clock to data tracking and mitigate the impact of power supply noise on maximum operating frequency. We prove the theory with measurements using a 130 nm processor as an experimental validation vehicle.

引用

页码：307 / 310

页数：4

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