Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI

被引：1

作者：

Kato, Shinichi ^{[1
]}

Watanabe, Minoru ^{[1
]}

机构：

[1] Shizuoka Univ, Hamamatsu, Shizuoka 4328561, Japan

来源：

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY | 2008年

关键词：

D O I：

10.1109/FPT.2008.4762422

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a novel inversion / non-inversion zero-overhead dynamic optically reconfigurable gate array that can extract good factors from architectures of both optically differential reconfigurable gate arrays and dynamic optically reconfigurable gate arrays. A full VLSI design using a 0.35 mu m CMOS process technology is presented. Based on that presentation, three factors are discussed: gate density; reconfiguration frequency per unit of laser power, optical power consumption.

引用

页码：377 / 380

页数：4

共 37 条

[1] An inversion/non-inversion dynamic optically reconfigurable gate array VLSI
Department of Electrical and Electronic Engineering, Shizuoka University, 3-5-1 Johoku, Hamamatsu, Shizuoka 432-8561, Japan
WSEAS Trans. Circuits Syst., 2009, 1 (11-20):
[2] Inversion/non-inversion dynamic optically reconfigurable gate array
Watanabe, Minoru
Nakajima, Mao
PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS: NEW ASPECTS OF CIRCUITS, 2008, : 249 - +
[3] A zero-overhead dynamic optically reconfigurable gate array
Watanabe, M
Kobayashi, F
FPT 05: 2005 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS, 2005, : 297 - 298
[4] Inversion/Non-inversion Implementation for an 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI
Kato, Shinichi
Watanabe, Minoru
EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, PROCEEDINGS, 2009, 5657 : 139 - 148
[5] Inversion/non-inversion reconfiguration scheme for a 0.18 μm CMOS process optically reconfigurable gate array VLSI
Watanabe, Takahiro
Watanabe, Minoru
2012 IEEE 55TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2012, : 117 - 120
[6] An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI
Watanabe, Minoru
20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2007, : 75 - 78
[7] A 1,632 gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
Watanabe, Minoru
Kobayashi, Fuminori
RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS, 2006, 3985 : 268 - 273
[8] A 0.35um CMOS 1,632-gate-count zero-overhead dynamic optically reconfigurable gate array VLSI
Watanabe, Minoru
Kobayashi, Fuminori
PROCEEDINGS OF THE ASP-DAC 2007, 2007, : 124 - +
[9] An 11,424-gate dynamic optically reconfigurable gate array VLSI
Nakajima, Mao
Watanabe, Minoru
PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, 2008, : 293 - 296
[10] Dynamic optically reconfigurable gate array
Department of Systems Innovation and Informatics, Kyushu Institute of Technology, 680-4 Kawazu, Iizuka, Fukuoka 820-8502, Japan
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 2006, 45 (4 B): : 3510 - 3515

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