An 11,424-gate dynamic optically reconfigurable gate array VLSI

被引：0

作者：

Nakajima, Mao ^{[1
]}

Watanabe, Minoru ^{[1
]}

机构：

[1] Shizuoka Univ, Hamamatsu, Shizuoka 4328561, Japan

来源：

PROCEEDINGS OF THE 2008 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY | 2008年

关键词：

D O I：

10.1109/FPT.2008.4762401

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A DORGA architecture has been proposed to increase gate density It uses the junction capacitance of photo-diodes as dynamic memory, thereby obviating the static configuration memory. This paper presents the world's largest 11,424 gate-count dynamic optically reconfigurable gale array (DORGA) VLSI fabricated on a 96.04 mm(2) chip using a 0.35 mu m three-metal CMOS process technology and a perfect optical system using a holographic memory. The advantages of this architecture arc, discussed in relation to the results described herein.

引用

页码：293 / 296

页数：4

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