High-speed LDPC Encoder Architecture for Digital Video Broadcasting Systems

被引：0

作者：

Lee, Inki ^{[1
]}

Oh, DeockGil ^{[1
]}

Kim, MinHyuk ^{[2
]}

Jung, Jiwon ^{[2
]}

机构：

[1] Elect & Telecommun Res Inst, Satellite & Wireless Convergence Res Dept, Taejon, South Korea

[2] Korea Maritime Univ, Elect Wave Engn Dept, Pusan, South Korea

来源：

2013 INTERNATIONAL CONFERENCE ON ICT CONVERGENCE (ICTC 2013): FUTURE CREATIVE CONVERGENCE TECHNOLOGIES FOR NEW ICT ECOSYSTEMS | 2013年

关键词：

DVB-S2; LDPC encoder; Memory;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a high-speed LDPC encoder architecture for the DVB-S2 standard. The proposed LDPC encoding architecture is based on parallel 360 bit-wise operations. The key issues for realizing a high speed are two kinds of index addresses and making efficient use of memory. We implemented a half-rate LDPC encoder on an FPGA, and confirmed that its maximum throughput is up to 10 Gbps with a 100 MHz clock.

引用

页码：608 / +

页数：2

共 50 条

[1] High Speed LDPC Encoder Architecture for Digital Video Broadcasting Systems
Jung, Ji Won
Park, Gun Yeol
COMPUTER APPLICATIONS FOR DATABASE, EDUCATION, AND UBIQUITOUS COMPUTING, 2012, 352 : 233 - 238
[2] Design of A High-speed Parallel LDPC Encoder
Wu, Guoqiang
Tan, Shujun
Zhang, Jianwei
JOURNAL OF COMPUTERS, 2013, 8 (08) : 1995 - 2002
[3] An Efficient GC-LDPC Encoder Architecture for High-Speed NAND Flash Applications
Bao, Binhao
Guan, Wu
Liang, Liping
Qiu, Xin
IEICE ELECTRONICS EXPRESS, 2024, 21 (02):
[4] Memory-efficient and high-speed LDPC encoder
Jung, Y.
Jung, Y.
Kim, J.
ELECTRONICS LETTERS, 2010, 46 (14) : 1035 - U108
[5] Efficient high-speed quasi-cyclic LDPC decoder architecture
Zhang, YP
Wang, ZF
Parhi, KK
CONFERENCE RECORD OF THE THIRTY-EIGHTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 2004, : 540 - 544
[6] VLSI Architecture of High Speed SAD for High Efficiency Video Coding (HEVC) Encoder
Joshi, Amit M.
Ansari, Mohd. Samar
Sahu, Chitrakant
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[7] A HIGH-SPEED PARALLEL ARCHITECTURE FOR RECURSIVE DIGITAL FILTERING
HAASE, J
AUER, E
HOFER, K
LUDER, E
AEU-ARCHIV FUR ELEKTRONIK UND UBERTRAGUNGSTECHNIK-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 1986, 40 (04): : 241 - 246
[8] Low Complexity and Reconfigurable LDPC Encoder for High-speed Satellite-to-ground Data Transmissions
Kang Jing
An Junshe
Wang Bingbing
JOURNAL OF ELECTRONICS & INFORMATION TECHNOLOGY, 2021, 43 (12) : 3727 - 3734
[9] Architecture and VLSI Realization of a High-Speed Programmable Decoder for LDPC Convolutional Codes
Tavares, Marcos B. S.
Kunze, Steffen
Matus, Emil
Fettweis, Gerhard P.
2008 INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, 2008, : 215 - 220
[10] RADIATION OF A SLOT IN HIGH-SPEED DIGITAL SYSTEMS
Nicolaescu, Mircea
Croitoru, Victor
Tuta, Leontin
REVUE ROUMAINE DES SCIENCES TECHNIQUES-SERIE ELECTROTECHNIQUE ET ENERGETIQUE, 2022, 67 (03): : 327 - 330

← 1 2 3 4 5 →