Low Complexity and Reconfigurable LDPC Encoder for High-speed Satellite-to-ground Data Transmissions

A new low complexity and reconfigurable Low Density Parity Check (LDPC) encoder design based on the Consultative Committee for Space Data Systems (CCSDS) standard is proposed to meet the high throughput, low latency and high reliability requirement for high-speed satellite-to-ground data transmission systems of Low Earth Orbit (LEO). This design is parallel reconfigurable by inserting 0 into information bits and splitting cyclic matrices, and analyzed the structural characteristics of different parallelism encoding. Benefitting from the parallel reconfiguration, the throughput is increased and the flexibility is guaranteed. Furthermore, using optimized shift register adder accumulators can reduce the hardware resources. The proposed encoder design is implemented on Xilinx FPGA. The experimental results show that the maximum encoding speed is up to 1 Gbps @125 MHz, and the normalized throughput is increased by 17.1% compared with the similar parallel encoder. And resources of registers and look-up tables are reduced by 13.7% and 14.8% respectively, compared with the existing encoder.