High-speed LDPC Encoder Architecture for Digital Video Broadcasting Systems

被引：0

作者：

Lee, Inki ^{[1
]}

Oh, DeockGil ^{[1
]}

Kim, MinHyuk ^{[2
]}

Jung, Jiwon ^{[2
]}

机构：

[1] Elect & Telecommun Res Inst, Satellite & Wireless Convergence Res Dept, Taejon, South Korea

[2] Korea Maritime Univ, Elect Wave Engn Dept, Pusan, South Korea

来源：

2013 INTERNATIONAL CONFERENCE ON ICT CONVERGENCE (ICTC 2013): FUTURE CREATIVE CONVERGENCE TECHNOLOGIES FOR NEW ICT ECOSYSTEMS | 2013年

关键词：

DVB-S2; LDPC encoder; Memory;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a high-speed LDPC encoder architecture for the DVB-S2 standard. The proposed LDPC encoding architecture is based on parallel 360 bit-wise operations. The key issues for realizing a high speed are two kinds of index addresses and making efficient use of memory. We implemented a half-rate LDPC encoder on an FPGA, and confirmed that its maximum throughput is up to 10 Gbps with a 100 MHz clock.

引用

页码：608 / +

页数：2

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