An Integrator-Based Pipelined ADC With Digital Calibration

被引：4

作者：

Wang, Dong ^{[1
]}

Keane, John P. ^{[1
]}

Hurst, Paul J. ^{[1
]}

Lewis, Stephen H. ^{[1
]}

机构：

[1] Univ Calif Davis, Davis, CA 95616 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2015年 / 62卷 / 09期

基金：

美国国家科学基金会;

关键词：

Adaptive calibration; complementary metal-oxide-semiconductor (CMOS) analog integrated circuits; data conversion; CONVERTER; MS/S; 16-BIT; 10-B;

D O I：

10.1109/TCSII.2015.2435514

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25-mu m CMOS prototype dissipates 140 mW and occupies an active area of 5 mm(2). At 40 megasamples/s (40MS/s), the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB.

引用

页码：831 / 835

页数：5

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