An On-Chip Jitter Tolerance Test Circuit for Mobile and Video Interfaces

被引：0

作者：

Kim, Ik-Hwan ^{[1
]}

Jung, Jae-Hong ^{[1
]}

Kim, Sang-Hoon ^{[1
]}

Chun, Jung-Hoon ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Seoul, South Korea

来源：

2016 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-ASIA (ICCE-ASIA) | 2016年

关键词：

on-chip jitter tolerance; phase-locked-loop; jitter injection;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We proposed an on-chip jitter injection circuit embedded in phase-locked-loop for jitter tolerance test of clock and data recovery circuit. The proposed jitter modulation block consists of divider, signal modulator, and modulating charge pump to inject the sinusoidal voltage to the VCO control voltage. Jitter modulation frequency and amplitude cover the jitter tolerance mask for DisplayPort v1.2 from 1 MHz to 100 MHz. The test circuit was implemented using a 28 nm CMOS technology for a 4 Gbps interface.

引用

页数：4

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