On-chip Reference-less Clock Jitter Measurement

This paper presents a novel on-chip clock jitter measurement scheme without the need of any reference entities. The proposed technique utilizes the degrading effect of jitter on performance metrics of a Continuous Time Sigma Delta Modulator based Analog to Digital Converter (CTSD ADC). The impact of jitter on modulator performance is very systematic and quantifiable. This coherent jitter influence on SNR (Signal to Noise Ratio) of the CTSD ADC is deployed into an architecture for in-situ jitter measurement during the operational, test or debug phase. The output response is analyzed on-chip using a simplified version of the sine-wave fitting algorithm to compute the SNR. The achieved performance is scalable with technology node and can in principle be increased as much as desired. High measurement resolutions less than 1pS can be achieved.