Area Efficient Parallel Median Filter Using Approximate Comparator and Faithful Adder

Approximate computing is a novel approach to design area-efficient arithmetic units for portable error resilient applications. In this work, the authors have proposed a parallel architecture for median filter targeting digital image processing. Proposed parallel median filter (PMF) uses pre-sorter and post-merge units to replace corrupted processing pixel (PP) with a median of pixels in the 3X3 processing window. Approximate compare and swap (CS) blocks that can trade off area at the expense of accuracy are proposed and used in the proposed PMF. Two variants of PMF are realised based on the implementation of approximate CS units in the pre-sorter and post-merge blocks. In PMF-design1, the authors use the exact CS unit in the pre-sorter and approximate CS unit in the post-merge block (hereafter referred to as P-EA) and in PMF-design2, they use approximate CS unit in both pre-sorter and post-merge blocks (hereafter referred to as P-AA). Functionality and accuracy efficacy of the proposed PMFs are verified with the image de-noising application. Synthesis with 90 nm application specific integrated chip technology revealed that to the least, proposed PMFs demonstrate 33.75 and 41.9% area-delay product and power-delay product reductions, respectively, compared to the standard median filter.