A reconfigurable Design-for-Debug infrastructure for SoCs

被引：173
|
作者：
Abramovici, Miron [1 ]
Bradley, Paul [1 ]
Dwarakanath, Kumar [1 ]
Levin, Peter [1 ]
Memmi, Gerard [1 ]
Miller, Dave [1 ]
机构：
[1] DAFCA Inc, 10 Speen St,2nd Floor, Framingham, MA 01701 USA
来源：
43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年
关键词：
verification; performance; design; economics; experimentation; silicon debug; at-speed debug; assertion-based debug; what-if experiments;
D O I：
10.1109/DAC.2006.238683
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.
引用
收藏
页码：7 / +
页数：3
相关论文
共 50 条
  • [1] How can the results of silicon debug justify the investment in design-for-debug infrastructure?
    Venkataraman, Srikanth
    [J]. 2007 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2007, : 1026 - 1026
  • [2] How can the results of silicon debug justify the investment in Design-for-Debug Infrastructure?
    Gottlieb, Bob
    [J]. 2007 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2007, : 1030 - 1030
  • [3] Survey of design-for-debug of VLSI
    Qian, Cheng
    Shen, Haihua
    Chen, Tianshi
    Chen, Yunji
    [J]. Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2012, 49 (01): : 21 - 34
  • [4] Design-for-debug: A vital aspect in education
    Nagvajara, Prawat
    Taskin, Baris
    [J]. 2007 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC SYSTEMS EDUCATION, PROCEEDINGS, 2007, : 65 - +
  • [5] Design-for-Debug Routing for FIB Probing
    Lee, Chia-Yi
    Li, Tai-Hung
    Chen, Tai-Chen
    [J]. 2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE), 2014,
  • [6] Secure Design-for-Debug for Systems-on-Chip
    Backer, Jerry
    Hely, David
    Karri, Ramesh
    [J]. 2015 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2015,
  • [7] Design-for-debug in hardware/software co-design
    Vranken, HPE
    Stevens, MPJ
    Segers, MTM
    [J]. PROCEEDINGS OF THE FIFTH INTERNATIONAL WORKSHOP ON HARDWARE/SOFTWARE CODESIGN (CODES/CASHE '97), 1997, : 35 - 39
  • [8] Design-for-Debug Architecture for Distributed Embedded Logic Analysis
    Ko, Ho Fai
    Kinsman, Adam B.
    Nicolici, Nicola
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 19 (08) : 1380 - 1393
  • [9] Design-for-debug to address next-generation SoC debug concerns
    Vermeulen, Bart
    [J]. 2007 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, 2007, : 1031 - 1031
  • [10] Exploiting Design-for-Debug for Flexible SoC Security Architecture
    Basak, Abhishek
    Bhunia, Swarup
    Ray, Sandip
    [J]. 2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2016,
12345