A reconfigurable Design-for-Debug infrastructure for SoCs

被引：173
|
作者：
Abramovici, Miron [1 ]
Bradley, Paul [1 ]
Dwarakanath, Kumar [1 ]
Levin, Peter [1 ]
Memmi, Gerard [1 ]
Miller, Dave [1 ]
机构：
[1] DAFCA Inc, 10 Speen St,2nd Floor, Framingham, MA 01701 USA
来源：
43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006 | 2006年
关键词：
verification; performance; design; economics; experimentation; silicon debug; at-speed debug; assertion-based debug; what-if experiments;
D O I：
10.1109/DAC.2006.238683
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters.
引用
收藏
页码：7 / +
页数：3
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