A Continuous Time ΔΣ ADC with Clock Timing Calibration

被引:0
|
作者
Tsai, Jen-Che [1 ]
Chen, Jhy-Rong [1 ]
Hsueh, Kang-Wei [1 ]
Chen, Mu-Jung [1 ]
机构
[1] MediaTek Inc, Hsinchu, Taiwan
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requirement of the adder for excess loop delay compensation. The ADC has been designed and fabricated in a 0.13um CMOS process. The ADC achieves 75dB dynamic range and 69dB peak signal-to-noise ratio (SNR) at 1MHz signal bandwidth and 64MHz sampling rate while dissipating 2.2mW from 1.2V supply.
引用
收藏
页码:365 / 368
页数:4
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