A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS

被引：0

作者：

Chen, Wei-Chih ^{[1
]}

Wen, Chin-Hua ^{[1
]}

Fu, Chin-Ming ^{[1
]}

Tsai, Tsung-Hsien ^{[1
]}

Chen, Yu-Chi ^{[1
]}

Huang, Wen-Hung ^{[1
]}

Tsai, Chien-Chun ^{[1
]}

Loke, Alvin L. S. ^{[1
]}

Hsieh, Kenny C-H ^{[1
]}

机构：

[1] TSMC, Hsinchu, Taiwan

来源：

2020 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2020年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a high-accuracy wideband quadrature clock generator (QCG) built in 5nm finFET CMOS. To achieve low power and high bandwidth, we employ an active poly phase filter (APPF) to generate the quadrature phases with 6dB gain boost and 30% bandwidth extension. The subsequent quadrature error corrector (QEC) and phase error detector (PED) corrects the APPF output phases with a phase interpolator (PI) to achieve <1 degrees quadrature error across 4-18GHz. At 18GHz, jitter integrated across 100kHz-1GHz and 100kHz-9GHz is respectively 148 and 218fs with 154fs(rms) phase jitter measured at 14GHz. The noise floor is below -138dBc/Hz at 1GHz offset. The QCG occupies 0.0017mm(2) and consumes only 21mW on a 1.0V supply for a FoM of 1.16mW/GHz

引用

页数：2

共 29 条

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