A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS

Wide-band quadrature phase clocks are of paramount importance in programmable digitally intensive wireless receivers and transmitters. However, existing solutions on the quadrature clock generators that support a wide frequency range exhibit inadequate phase error, poor phase noise performance, and moreover, they are power hungry. To address these issues, a polyphase filter-based phase interpolation architecture is proposed in this work to generate four-phase quadrature clocks. The linear phase interpolation of the clock phases generated by polyphase filters results in self-aligned quadrature clocks with adequate phase error performance. The proposed quadrature clock generation employs passive polyphase filters and inverters for phase interpolation, makes the work power efficient. The proposed architecture operating over the frequency range of 1-6 GHz is realized in 1.2 V, 65 nm CMOS, and it occupies an active area of 0.012 mm(2). The performance results show that the phase error is less than +/- 1. and phase noise is less than -133 dBc/Hz at an offset of 1 MHz for the frequency range of 1-6 GHz with a power consumption of less than one mW.