A 2.2-2.4 GHz Self-aligned Sub-harmonically Injection-locked Phase-locked Loop using 65 nm CMOS Process

被引：0

作者：

Yeh, Yen-Liang ^{[1
]}

Lu, Cheng-Han ^{[1
]}

Li, Meng-Han ^{[1
]}

Chang, Hong-Yeh ^{[1
]}

Chen, Kevin ^{[2
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Jhongli 32001, Taiwan

[2] ITRI, Informat & Commun Res Labs, Hsinchu 310, Taiwan

来源：

2014 9TH EUROPEAN MICROWAVE INTEGRATED CIRCUIT CONFERENCE (EUMIC) | 2014年

关键词：

CMOS; DLL; low jitter; low phase noise; PLL; VCO; CLOCK MULTIPLIER; NOISE; RANGE; PLL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 2.2-2.4 GHz self-aligned sub-harmonically injection-locked phase-locked loop (PLL) using 65 nm CMOS process is presented in this paper. A delay-locked loop is employed in the proposed PLL to automatically align the phase difference between the injection signal and the sub-harmonically injection-locked voltage controlled oscillator. At 2.3 GHz, the measured phase noises at 1 kHz, 10 kHz, 100 kHz, and 1 MHz offset are better than -110, -112, -122 and -128.4 dBc/Hz, respectively, with an rms jitter of 228 fs. This work demonstrates low phase noise, low jitter, and good robustness over frequency and temperature variations.

引用

页码：269 / 272

页数：4

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