A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth

被引：11

作者：

Jin, Xuefan ^{[1
,2
]}

Park, Woosung ^{[1
]}

Kang, Dong-Seok ^{[1
]}

Ko, Youngjun ^{[1
]}

Kwon, Kee-Won ^{[1
]}

Chun, Jung-Hoon ^{[1
]}

机构：

[1] Sungkyunkwan Univ, Coll Informat & Commun Engn, Suwon 16419, South Korea

[2] LG Elect, Seoul 06772, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2020年 / 55卷 / 10期

基金：

新加坡国家研究基金会;

关键词：

Injection-locked phase-locked loop (ILPLL); injection-locked ring oscillator (ILRO); phase-locked loop (PLL); ring oscillator; self-calibrated injection pulsewidth; self-calibrated injection timing; NOISE; PLL;

D O I：

10.1109/JSSC.2020.3005806

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 4-GHz sub-harmonically injection-locked phase-locked loop (ILPLL) with on-chip calibration is presented. The injection timing and pulsewidth of the injected pulse are self-calibrated to achieve low phase noise. The phase noise of the proposed ILPLL was -112.3 dBc/Hz at 1-MHz offset frequency, whereas that of the conventional PLL was -104.8 dBc/Hz. The measured integrated jitter from 10 kHz to 30 MHz was 710 fs, and the corresponding reference spur level was -61.6 dBc with the proposed calibration technique. Fabricated in a 28-nm CMOS process, the proposed ILPLL occupies 0.09 mm(2). Operating at 4 GHz, it consumes 11.4 mW from a 1.0-V power supply.

引用

页码：2724 / 2733

页数：10

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