A 4-to-18GHz Active Poly Phase Filter Quadrature Clock Generator with Phase Error Correction in 5nm CMOS

被引：0

作者：

Chen, Wei-Chih ^{[1
]}

Wen, Chin-Hua ^{[1
]}

Fu, Chin-Ming ^{[1
]}

Tsai, Tsung-Hsien ^{[1
]}

Chen, Yu-Chi ^{[1
]}

Huang, Wen-Hung ^{[1
]}

Tsai, Chien-Chun ^{[1
]}

Loke, Alvin L. S. ^{[1
]}

Hsieh, Kenny C-H ^{[1
]}

机构：

[1] TSMC, Hsinchu, Taiwan

来源：

2020 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2020年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a high-accuracy wideband quadrature clock generator (QCG) built in 5nm finFET CMOS. To achieve low power and high bandwidth, we employ an active poly phase filter (APPF) to generate the quadrature phases with 6dB gain boost and 30% bandwidth extension. The subsequent quadrature error corrector (QEC) and phase error detector (PED) corrects the APPF output phases with a phase interpolator (PI) to achieve <1 degrees quadrature error across 4-18GHz. At 18GHz, jitter integrated across 100kHz-1GHz and 100kHz-9GHz is respectively 148 and 218fs with 154fs(rms) phase jitter measured at 14GHz. The noise floor is below -138dBc/Hz at 1GHz offset. The QCG occupies 0.0017mm(2) and consumes only 21mW on a 1.0V supply for a FoM of 1.16mW/GHz

引用

页数：2

共 29 条

[21] A 0.0558-mm2 0.05-0.9GHz Low-Power Multi-phase Non-overlap Clock Generator in 40 nm CMOS
Li, Zhigang
Wang, Xiaofei
Jin, Jing
2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON), 2019,
[22] A 25-35 GHz 5-bit digital attenuator with low RMS amplitude error and low phase variation in 65 nm CMOS
Li, An'an
Ding, Yingtao
Chen, Zhiming
Chi, Baoyong
IEICE ELECTRONICS EXPRESS, 2019, 16 (15):
[23] A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS
Chen, Bo-Fan
Li, Zhi-Qun
Shi, Wei
Yao, Yan
Xia, Zhi-Ying
Qiu, Bing-Yan
Ji, Hao
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 32 (03) : 530 - 541
[24] A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation
Min, Seungkee
Copani, Tino
Kiaei, Sayfe
Bakkaloglu, Bertan
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (05) : 1151 - 1160
[25] A miniaturized 28 GHz 4-bit phase shifter in 65 nm LP CMOS for multi-channel 5-G radios
Lee, Junghwan
Seo, Munkyo
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2019, 61 (02) : 381 - 385
[26] A 28GHz Area-Efficient CMOS Vector-Summing Phase Shifter Utilizing Phase-Inverting Type-I Poly-Phase Filter for 5G New Radio
Tang, Minzhe
Zhang, Yi
Pang, Jian
Shirane, Atsushi
Okada, Kenichi
ESSCIRC 2022- IEEE 48TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC), 2022, : 333 - 336
[27] Multi-Phase Clock Path Circuit up to 57 GHz Including 5 bit Programmable Phase Interpolators for Time-Interleaved Broadband Data Converters in a 28 nm FD-SOI CMOS Technology
Widmann, Daniel
Tannert, Tobias
Du, Xuan-Quang
Groezing, Markus
Berroth, Manfred
2021 16TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC 2021), 2021, : 177 - 180
[28] A 55-70GHz Two-Stage Tunable Polyphase Filter with Feedback Control for Quadrature Generation with <2° and <0.32dB Phase/Amplitude Imbalance in 28nm CMOS Process
Zhang, Tong
Taghivand, Mazhareddin
Rudell, Jacques C.
ESSCIRC CONFERENCE 2015 - 41ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC), 2015, : 60 - 63
[29] A 78.8-92.8 GHz 4-bit 0-360° Active Phase Shifter in 28nm FDSOI CMOS with 2.3 dB Average Peak Gain
Pepe, Domenico
Zito, Domenico
ESSCIRC CONFERENCE 2015 - 41ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC), 2015, : 64 - 67

← 1 2 3 →